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Memory Interleave Enabler Tech Notes

Memory Interleave Enabler
for VIA Chipsets:
Technical notes

Copyright (C) 2001, George E. Breese. All Rights Reserved.

Version 0.12 4/2/01

Important: This product CAN DAMAGE A COMPUTER.

License: This software is licensed, not sold. The author of this product has granted you a license to use this product, subject to the following conditions. By possessing, using, or attempting to use this product, you assume all liability for its use. You agree never to take legal action, civil or criminal, against its author for any reason. You may redistribute this product in its original form only. You may not charge money for distribution of the product, unless all such charges are remitted to the author immediately upon payment. The author retains ownership of all intellectual properties embodied in this product.

Revision History

Version 0.12 April 2, 2001

This is the current version. This version is identical to v0.11 except that it enables three fewer features. These features did not seem to affect performance on a Pro133, but were possibly causing Pro133 motherboards to be less stable.

Support for KT133 and MVP4 chipsets is based on documentation only, and is untested. KX133 support was successful on a Biostar M7MKE, and resulted in a 32% improvement in SiSoft Sandra memory benchmark numbers.

NOTE: This version of the driver does not detect 16-megabit RAM, and always enables 4-way interleave in any SDRAM. VIA chipsets only support 2-way interleave on 16-megabit RAM modules.

Version 0.11 March 31, 2001

This version contained the first support for MVP3, MVP4, KX133, and KT133 chipsets. It detects and avoids interleaving "Fast Page" and EDO RAM, for which VIA has no support.

Support for KT133 and MVP4 chipsets is based on documentation only, and is untested.

This version of the driver had a potential bug. It set DRAM flags that may have caused memory to be less stable on Apollo Pro Plus and Pro133 series motherboards.

  • CPU DRAM prefetch depth: was set to 4-level
  • CPU DRAM read while snoop: was enabled
  • CPU DRAM post-write depth: was set to 4-level

Version 0.1 February 28, 2001

This version was the initial release. It supported the VIA Apollo Pro133 and Pro133A chipsets only. It had the following known bugs:

  • It failed to enable the "read around write" bit of the chipset, with the result that some users saw no improvement. Users could enable "read around write" in their BIOS if needed.
  • The documentation showed Sandra benchmark numbers that showed improvement on a ChainTech 6ATA2 motherboard, but the numbers were taken from a beta copy of the driver that enabled "read around write". The 6ATA2 board did improve when using the official v0.1 release, as follows:
    Before: 124 ALU / 128 FP
    After: 188 ALU / 201 FP

Technical Information

The Apollo Pro series need more than just memory interleaving in order to maximize their memory performance. The following register settings are applied to all Apollo Pro-series chips by the driver:

  • In-Order Queue depth: set to 4-level
  • Read-around-write: Enabled

In addition, all of the supported chipsets receive the following settings.

  • Bank active page control: set to "any bank"
  • Interleave: Set to "4-way" for any SDRAM or DDR-SDRAM bank of memory, based on the memory-configuration register

The driver reads PCI Device #0 and checks it for vendor ID and model ID before proceeding. The vendor ID is 0x1106 for VIA, and the model IDs 0x0597, 0x0598, 0x0691, 0x0391, and 0x0305 are currently supported.

This driver only changes the relevant bits of each register.

Contact Information

If you wish to offer feedback on this driver, send email to [email protected] . Please note that I do not check this mailbox frequently, and I do not answer questions about installation or use of this driver.


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